Field of the Invention
The present invention relates to a winner-take-all (WTA) analog circuit, and more particularly, to a reject signal for a WTA circuit.
Artificial neural networks and fuzzy logic are very effective in processing complex scientific, and engineering problems such as pattern classification since both of them are non-parametric, and need no mathematical model. Their massive parallelism, learning ability, adaptivity and fault tolerance make them more attractive in the field of pattern information processing. Although software simulations based on theory of artificial neural network, and fuzzy logic paradigms can be performed in conventional Von Neumann machines, the simulations usually take too much time for practical applications. Recently many significant advances in electronic implementation of neural networks and fuzzy logic have been achieved. Winner-take-all networks for selecting the most prominent one from N elements are central processing components in most model of neural networks such as Hamming neural network, ART (Adaptive Resonance Theory) model, SOFM (Self-organized Feature Mapping) model and fuzzy processors. It can be regarded as 1-WTA if only one prominent element is selected in one time, we call it k-WTA networks if it can select k maximum from N elements.
The WTA circuit operates by having a plurality of inputs with corresponding outputs. Using an example of a 1-WTA configuration, the circuit will select the current input that has a maximum magnitude (hence winner-take-all), and switch its corresponding output to a high voltage state. The other voltage outputs will be at a low voltage state.
In a normal k-WTA network the system will choose the most prominent element(s) of N inputs. If one of the elements is in a rising condition however it can be very difficult for the system to determine which element(s) are the most prominent. In the previous art if a WTA network is presented with two inputs that are both at similar current levels the circuit could possibly choose the wrong input as being the most prominent element or could simply reject both signals even though a definable difference exists. This limitation becomes especially important on circuits with highly varying inputs or noise.
Therefore a need exists for a k-WTA network that has the ability to correctly choose or reject two similar inputs by sending out a reject signal.
The invention as described herein provides a circuit apparatus for comparing two current inputs from a WTA circuit to a threshold current to create a reject signal if needed to assist in the decision criteria of a winner-take-all network. The threshold current is adjustable. The circuit then sends out a voltage output depending on the a comparison which can act as a reject signal. The invention also provides a WTA circuit with weighted inputs and the ability to select between a 1-WTA, and a 2-WTA configuration.
The circuit compares the two input currents from the WTA circuit by using NMOS transistors which perform electrical mathematical functions by manipulating the currents. The end result is that the difference of the two currents is compared with a reference current. The output voltage level which has two logical states is then set either high or low to indicate if the two inputs are definable or if their values are too close according to the threshold current to determine which current input is the most prominent.
The invention therefore solves the problems of prior art by being capable of properly selecting current levels or rejecting current levels which are too close in value, with a voltage reject signal. This allows for the proper decision criteria for the determination of a most prominent input.
These and other features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.